/**
 * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
 *
 *  SPDX-License-Identifier: Apache-2.0 OR MIT
 */
#pragma once

#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

/** INTERRUPT_CORE0_SYS_ICM_INTR_MAP_REG register
 *  SYS_ICM_INTR mapping register
 */
#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
/** INTERRUPT_CORE0_SYS_ICM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP_M  (INTERRUPT_CORE0_SYS_ICM_INTR_MAP_V << INTERRUPT_CORE0_SYS_ICM_INTR_MAP_S)
#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP_S  0
/** INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_REG register
 *  AXI_PERF_MON_INTR mapping register
 */
#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
/** INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_V << INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_S)
#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_S  0
/** INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_REG register
 *  USB_DEVICE_INTR mapping register
 */
#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
/** INTERRUPT_CORE0_USB_DEVICE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_M  (INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_V << INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_S  0
/** INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_REG register
 *  SDIO_HOST_INTR mapping register
 */
#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc)
/** INTERRUPT_CORE0_SDIO_HOST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_M  (INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_V << INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_S)
#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_S  0
/** INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_SPI2_INTR_MAP_REG register
 *  SPI2_INTR mapping register
 */
#define INTERRUPT_CORE0_SPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
/** INTERRUPT_CORE0_SPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_SPI2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_SPI2_INTR_MAP_M  (INTERRUPT_CORE0_SPI2_INTR_MAP_V << INTERRUPT_CORE0_SPI2_INTR_MAP_S)
#define INTERRUPT_CORE0_SPI2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_SPI2_INTR_MAP_S  0
/** INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_SPI3_INTR_MAP_REG register
 *  SPI3_INTR mapping register
 */
#define INTERRUPT_CORE0_SPI3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
/** INTERRUPT_CORE0_SPI3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_SPI3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_SPI3_INTR_MAP_M  (INTERRUPT_CORE0_SPI3_INTR_MAP_V << INTERRUPT_CORE0_SPI3_INTR_MAP_S)
#define INTERRUPT_CORE0_SPI3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_SPI3_INTR_MAP_S  0
/** INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_I2S0_INTR_MAP_REG register
 *  I2S0_INTR mapping register
 */
#define INTERRUPT_CORE0_I2S0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
/** INTERRUPT_CORE0_I2S0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_I2S0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_I2S0_INTR_MAP_M  (INTERRUPT_CORE0_I2S0_INTR_MAP_V << INTERRUPT_CORE0_I2S0_INTR_MAP_S)
#define INTERRUPT_CORE0_I2S0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_I2S0_INTR_MAP_S  0
/** INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register
 *  I2S1_INTR mapping register
 */
#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c)
/** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_I2S1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_I2S1_INTR_MAP_M  (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S)
#define INTERRUPT_CORE0_I2S1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_I2S1_INTR_MAP_S  0
/** INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register
 *  UHCI0_INTR mapping register
 */
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_UHCI0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S)
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
/** INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register
 *  UART0_INTR mapping register
 */
#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_UART0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_UART0_INTR_MAP_M  (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S)
#define INTERRUPT_CORE0_UART0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_UART0_INTR_MAP_S  0
/** INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register
 *  UART1_INTR mapping register
 */
#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_UART1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_UART1_INTR_MAP_M  (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S)
#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
/** INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_UART2_INTR_MAP_REG register
 *  UART2_INTR mapping register
 */
#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c)
/** INTERRUPT_CORE0_UART2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_UART2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_UART2_INTR_MAP_M  (INTERRUPT_CORE0_UART2_INTR_MAP_V << INTERRUPT_CORE0_UART2_INTR_MAP_S)
#define INTERRUPT_CORE0_UART2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_UART2_INTR_MAP_S  0
/** INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_UART3_INTR_MAP_REG register
 *  UART3_INTR mapping register
 */
#define INTERRUPT_CORE0_UART3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
/** INTERRUPT_CORE0_UART3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_UART3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_UART3_INTR_MAP_M  (INTERRUPT_CORE0_UART3_INTR_MAP_V << INTERRUPT_CORE0_UART3_INTR_MAP_S)
#define INTERRUPT_CORE0_UART3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_UART3_INTR_MAP_S  0
/** INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LCD_CAM_INTR_MAP_REG register
 *  LCD_CAM_INTR mapping register
 */
#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
/** INTERRUPT_CORE0_LCD_CAM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP_M  (INTERRUPT_CORE0_LCD_CAM_INTR_MAP_V << INTERRUPT_CORE0_LCD_CAM_INTR_MAP_S)
#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP_S  0
/** INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PWM0_INTR_MAP_REG register
 *  PWM0_INTR mapping register
 */
#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
/** INTERRUPT_CORE0_PWM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PWM0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PWM0_INTR_MAP_M  (INTERRUPT_CORE0_PWM0_INTR_MAP_V << INTERRUPT_CORE0_PWM0_INTR_MAP_S)
#define INTERRUPT_CORE0_PWM0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PWM0_INTR_MAP_S  0
/** INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PWM1_INTR_MAP_REG register
 *  PWM1_INTR mapping register
 */
#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c)
/** INTERRUPT_CORE0_PWM1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PWM1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PWM1_INTR_MAP_M  (INTERRUPT_CORE0_PWM1_INTR_MAP_V << INTERRUPT_CORE0_PWM1_INTR_MAP_S)
#define INTERRUPT_CORE0_PWM1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PWM1_INTR_MAP_S  0
/** INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PWM2_INTR_MAP_REG register
 *  PWM2_INTR mapping register
 */
#define INTERRUPT_CORE0_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
/** INTERRUPT_CORE0_PWM2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PWM2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PWM2_INTR_MAP_M  (INTERRUPT_CORE0_PWM2_INTR_MAP_V << INTERRUPT_CORE0_PWM2_INTR_MAP_S)
#define INTERRUPT_CORE0_PWM2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PWM2_INTR_MAP_S  0
/** INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PWM3_INTR_MAP_REG register
 *  PWM3_INTR mapping register
 */
#define INTERRUPT_CORE0_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
/** INTERRUPT_CORE0_PWM3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PWM3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PWM3_INTR_MAP_M  (INTERRUPT_CORE0_PWM3_INTR_MAP_V << INTERRUPT_CORE0_PWM3_INTR_MAP_S)
#define INTERRUPT_CORE0_PWM3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PWM3_INTR_MAP_S  0
/** INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register
 *  CAN0_INTR mapping register
 */
#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
/** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CAN0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CAN0_INTR_MAP_M  (INTERRUPT_CORE0_CAN0_INTR_MAP_V << INTERRUPT_CORE0_CAN0_INTR_MAP_S)
#define INTERRUPT_CORE0_CAN0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CAN0_INTR_MAP_S  0
/** INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG register
 *  CAN0_TIMER_INTR mapping register
 */
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c)
/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_V << INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_S)
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_S  0
/** INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CAN1_INTR_MAP_REG register
 *  CAN1_INTR mapping register
 */
#define INTERRUPT_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
/** INTERRUPT_CORE0_CAN1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CAN1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CAN1_INTR_MAP_M  (INTERRUPT_CORE0_CAN1_INTR_MAP_V << INTERRUPT_CORE0_CAN1_INTR_MAP_S)
#define INTERRUPT_CORE0_CAN1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CAN1_INTR_MAP_S  0
/** INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_REG register
 *  CAN1_TIMER_INTR mapping register
 */
#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
/** INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_V << INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_S)
#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_S  0
/** INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register
 *  RMT_INTR mapping register
 */
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_RMT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_RMT_INTR_MAP_M  (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S)
#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
/** INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_I2C0_INTR_MAP_REG register
 *  I2C0_INTR mapping register
 */
#define INTERRUPT_CORE0_I2C0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c)
/** INTERRUPT_CORE0_I2C0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_I2C0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_I2C0_INTR_MAP_M  (INTERRUPT_CORE0_I2C0_INTR_MAP_V << INTERRUPT_CORE0_I2C0_INTR_MAP_S)
#define INTERRUPT_CORE0_I2C0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_I2C0_INTR_MAP_S  0
/** INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_I2C1_INTR_MAP_REG register
 *  I2C1_INTR mapping register
 */
#define INTERRUPT_CORE0_I2C1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
/** INTERRUPT_CORE0_I2C1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_I2C1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_I2C1_INTR_MAP_M  (INTERRUPT_CORE0_I2C1_INTR_MAP_V << INTERRUPT_CORE0_I2C1_INTR_MAP_S)
#define INTERRUPT_CORE0_I2C1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_I2C1_INTR_MAP_S  0
/** INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_REG register
 *  TIMERGRP0_T0_INTR mapping register
 */
#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
/** INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_S)
#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_S  0
/** INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_REG register
 *  TIMERGRP0_T1_INTR mapping register
 */
#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
/** INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_S)
#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_S  0
/** INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_REG register
 *  TIMERGRP0_WDT_INTR mapping register
 */
#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
/** INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_S)
#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_S  0
/** INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_REG register
 *  TIMERGRP1_T0_INTR mapping register
 */
#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
/** INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_S)
#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_S  0
/** INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_REG register
 *  TIMERGRP1_T1_INTR mapping register
 */
#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
/** INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_S)
#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_S  0
/** INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_REG register
 *  TIMERGRP1_WDT_INTR mapping register
 */
#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
/** INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_S)
#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_S  0
/** INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LEDC0_INTR_MAP_REG register
 *  LEDC0_INTR mapping register
 */
#define INTERRUPT_CORE0_LEDC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c)
/** INTERRUPT_CORE0_LEDC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LEDC0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LEDC0_INTR_MAP_M  (INTERRUPT_CORE0_LEDC0_INTR_MAP_V << INTERRUPT_CORE0_LEDC0_INTR_MAP_S)
#define INTERRUPT_CORE0_LEDC0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LEDC0_INTR_MAP_S  0
/** INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LEDC1_INTR_MAP_REG register
 *  LEDC1_INTR mapping register
 */
#define INTERRUPT_CORE0_LEDC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
/** INTERRUPT_CORE0_LEDC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LEDC1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LEDC1_INTR_MAP_M  (INTERRUPT_CORE0_LEDC1_INTR_MAP_V << INTERRUPT_CORE0_LEDC1_INTR_MAP_S)
#define INTERRUPT_CORE0_LEDC1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LEDC1_INTR_MAP_S  0
/** INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
 *  SYSTIMER_TARGET0_INTR mapping register
 */
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
 *  SYSTIMER_TARGET1_INTR mapping register
 */
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
 *  SYSTIMER_TARGET2_INTR mapping register
 */
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_REG register
 *  AHB_PDMA_IN_CH0_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_REG register
 *  AHB_PDMA_IN_CH1_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_REG register
 *  AHB_PDMA_IN_CH2_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_REG register
 *  AHB_PDMA_IN_CH3_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_REG register
 *  AHB_PDMA_IN_CH4_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_REG register
 *  AHB_PDMA_OUT_CH0_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4)
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_REG register
 *  AHB_PDMA_OUT_CH1_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8)
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_REG register
 *  AHB_PDMA_OUT_CH2_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_REG register
 *  AHB_PDMA_OUT_CH3_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0)
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_REG register
 *  AHB_PDMA_OUT_CH4_INTR mapping register
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4)
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_S  0
/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG register
 *  ASRC_CHNL0_INTR mapping register
 */
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8)
/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_M  (INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_V << INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_S)
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_S  0
/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG register
 *  ASRC_CHNL1_INTR mapping register
 */
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc)
/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_M  (INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_V << INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_S)
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_S  0
/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_REG register
 *  AXI_PDMA_IN_CH0_INTR mapping register
 */
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_S)
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_S  0
/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_REG register
 *  AXI_PDMA_IN_CH1_INTR mapping register
 */
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_S)
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_S  0
/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_REG register
 *  AXI_PDMA_IN_CH2_INTR mapping register
 */
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_S)
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_S  0
/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_REG register
 *  AXI_PDMA_OUT_CH0_INTR mapping register
 */
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_S)
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_S  0
/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_REG register
 *  AXI_PDMA_OUT_CH1_INTR mapping register
 */
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_S)
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_S  0
/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_REG register
 *  AXI_PDMA_OUT_CH2_INTR mapping register
 */
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_S)
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_S  0
/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_RSA_INTR_MAP_REG register
 *  RSA_INTR mapping register
 */
#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
/** INTERRUPT_CORE0_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_RSA_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_RSA_INTR_MAP_M  (INTERRUPT_CORE0_RSA_INTR_MAP_V << INTERRUPT_CORE0_RSA_INTR_MAP_S)
#define INTERRUPT_CORE0_RSA_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_RSA_INTR_MAP_S  0
/** INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_AES_INTR_MAP_REG register
 *  AES_INTR mapping register
 */
#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_AES_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_AES_INTR_MAP_M  (INTERRUPT_CORE0_AES_INTR_MAP_V << INTERRUPT_CORE0_AES_INTR_MAP_S)
#define INTERRUPT_CORE0_AES_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_AES_INTR_MAP_S  0
/** INTERRUPT_CORE0_AES_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_AES_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register
 *  SHA_INTR mapping register
 */
#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_SHA_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_SHA_INTR_MAP_M  (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S)
#define INTERRUPT_CORE0_SHA_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_SHA_INTR_MAP_S  0
/** INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register
 *  ECC_INTR mapping register
 */
#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_ECC_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_ECC_INTR_MAP_M  (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S)
#define INTERRUPT_CORE0_ECC_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_ECC_INTR_MAP_S  0
/** INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register
 *  ECDSA_INTR mapping register
 */
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8)
/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_ECDSA_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M  (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S)
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S  0
/** INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_KM_INTR_MAP_REG register
 *  KM_INTR mapping register
 */
#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec)
/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_KM_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_KM_INTR_MAP_M  (INTERRUPT_CORE0_KM_INTR_MAP_V << INTERRUPT_CORE0_KM_INTR_MAP_S)
#define INTERRUPT_CORE0_KM_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_KM_INTR_MAP_S  0
/** INTERRUPT_CORE0_KM_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_KM_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_RMA_INTR_MAP_REG register
 *  RMA_INTR mapping register
 */
#define INTERRUPT_CORE0_RMA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0)
/** INTERRUPT_CORE0_RMA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_RMA_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_RMA_INTR_MAP_M  (INTERRUPT_CORE0_RMA_INTR_MAP_V << INTERRUPT_CORE0_RMA_INTR_MAP_S)
#define INTERRUPT_CORE0_RMA_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_RMA_INTR_MAP_S  0
/** INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_GPIO_INTR0_MAP_REG register
 *  GPIO_INTR0 mapping register
 */
#define INTERRUPT_CORE0_GPIO_INTR0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4)
/** INTERRUPT_CORE0_GPIO_INTR0_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_GPIO_INTR0_MAP    0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTR0_MAP_M  (INTERRUPT_CORE0_GPIO_INTR0_MAP_V << INTERRUPT_CORE0_GPIO_INTR0_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTR0_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTR0_MAP_S  0
/** INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_M  (INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_V << INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_S)
#define INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_GPIO_INTR1_MAP_REG register
 *  GPIO_INTR1 mapping register
 */
#define INTERRUPT_CORE0_GPIO_INTR1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8)
/** INTERRUPT_CORE0_GPIO_INTR1_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_GPIO_INTR1_MAP    0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTR1_MAP_M  (INTERRUPT_CORE0_GPIO_INTR1_MAP_V << INTERRUPT_CORE0_GPIO_INTR1_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTR1_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTR1_MAP_S  0
/** INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_M  (INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_V << INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_S)
#define INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_GPIO_INTR2_MAP_REG register
 *  GPIO_INTR2 mapping register
 */
#define INTERRUPT_CORE0_GPIO_INTR2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc)
/** INTERRUPT_CORE0_GPIO_INTR2_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_GPIO_INTR2_MAP    0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTR2_MAP_M  (INTERRUPT_CORE0_GPIO_INTR2_MAP_V << INTERRUPT_CORE0_GPIO_INTR2_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTR2_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTR2_MAP_S  0
/** INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_M  (INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_V << INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_S)
#define INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_GPIO_INTR3_MAP_REG register
 *  GPIO_INTR3 mapping register
 */
#define INTERRUPT_CORE0_GPIO_INTR3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
/** INTERRUPT_CORE0_GPIO_INTR3_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_GPIO_INTR3_MAP    0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTR3_MAP_M  (INTERRUPT_CORE0_GPIO_INTR3_MAP_V << INTERRUPT_CORE0_GPIO_INTR3_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTR3_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTR3_MAP_S  0
/** INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_M  (INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_V << INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_S)
#define INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
 *  CPU_INTR_FROM_CPU_0 mapping register
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
 *  CPU_INTR_FROM_CPU_1 mapping register
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
 *  CPU_INTR_FROM_CPU_2 mapping register
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
 *  CPU_INTR_FROM_CPU_3 mapping register
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register
 *  CACHE_INTR mapping register
 */
#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CACHE_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CACHE_INTR_MAP_M  (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S)
#define INTERRUPT_CORE0_CACHE_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CACHE_INTR_MAP_S  0
/** INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register
 *  CPU_APM_M0_INTR mapping register
 */
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S)
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S  0
/** INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register
 *  CPU_APM_M1_INTR mapping register
 */
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S)
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S  0
/** INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG register
 *  CPU_APM_M2_INTR mapping register
 */
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_S)
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_S  0
/** INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG register
 *  CPU_APM_M3_INTR mapping register
 */
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_S)
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_S  0
/** INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG register
 *  HP_MEM_APM_M0_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG register
 *  HP_MEM_APM_M1_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG register
 *  HP_MEM_APM_M2_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG register
 *  HP_MEM_APM_M3_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_REG register
 *  HP_MEM_APM_M4_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
/** INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_REG register
 *  HP_MEM_APM_M5_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
/** INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_REG register
 *  CPU_PERI0_TIMEOUT_INTR mapping register
 */
#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
/** INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_S)
#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_S  0
/** INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_REG register
 *  CPU_PERI1_TIMEOUT_INTR mapping register
 */
#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
/** INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_S)
#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_S  0
/** INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_REG register
 *  HP_PERI0_TIMEOUT_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
/** INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_REG register
 *  HP_PERI1_TIMEOUT_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
/** INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register
 *  HP_APM_M0_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register
 *  HP_APM_M1_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register
 *  HP_APM_M2_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register
 *  HP_APM_M3_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c)
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register
 *  HP_APM_M4_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_REG register
 *  HP_APM_M5_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
/** INTERRUPT_CORE0_HP_APM_M5_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_REG register
 *  HP_APM_M6_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
/** INTERRUPT_CORE0_HP_APM_M6_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_REG register
 *  HP_PERI0_PMS_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c)
/** INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_REG register
 *  HP_PERI1_PMS_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
/** INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_REG register
 *  CPU0_PERI_PMS_INTR mapping register
 */
#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
/** INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_M  (INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_S)
#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_S  0
/** INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_REG register
 *  CPU1_PERI_PMS_INTR mapping register
 */
#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
/** INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_M  (INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_S)
#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_S  0
/** INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_REG register
 *  FLASH_MSPI_INTR mapping register
 */
#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c)
/** INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_M  (INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_V << INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_S)
#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_S  0
/** INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LPI_INTR_MAP_REG register
 *  LPI_INTR mapping register
 */
#define INTERRUPT_CORE0_LPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
/** INTERRUPT_CORE0_LPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LPI_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LPI_INTR_MAP_M  (INTERRUPT_CORE0_LPI_INTR_MAP_V << INTERRUPT_CORE0_LPI_INTR_MAP_S)
#define INTERRUPT_CORE0_LPI_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LPI_INTR_MAP_S  0
/** INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PMT_INTR_MAP_REG register
 *  PMT_INTR mapping register
 */
#define INTERRUPT_CORE0_PMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
/** INTERRUPT_CORE0_PMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PMT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PMT_INTR_MAP_M  (INTERRUPT_CORE0_PMT_INTR_MAP_V << INTERRUPT_CORE0_PMT_INTR_MAP_S)
#define INTERRUPT_CORE0_PMT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PMT_INTR_MAP_S  0
/** INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_SBD_INTR_MAP_REG register
 *  SBD_INTR mapping register
 */
#define INTERRUPT_CORE0_SBD_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
/** INTERRUPT_CORE0_SBD_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_SBD_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_SBD_INTR_MAP_M  (INTERRUPT_CORE0_SBD_INTR_MAP_V << INTERRUPT_CORE0_SBD_INTR_MAP_S)
#define INTERRUPT_CORE0_SBD_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_SBD_INTR_MAP_S  0
/** INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_REG register
 *  USB_OTGHS_INTR mapping register
 */
#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c)
/** INTERRUPT_CORE0_USB_OTGHS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_M  (INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_V << INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_S  0
/** INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_REG register
 *  USB_OTGHS_ENDP_MULTI_PROC_INTR mapping register
 */
#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
/** INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_M  (INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_S  0
/** INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL : R/W; bitpos: [9:8];
 *  default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_JPEG_INTR_MAP_REG register
 *  JPEG_INTR mapping register
 */
#define INTERRUPT_CORE0_JPEG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
/** INTERRUPT_CORE0_JPEG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_JPEG_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_JPEG_INTR_MAP_M  (INTERRUPT_CORE0_JPEG_INTR_MAP_V << INTERRUPT_CORE0_JPEG_INTR_MAP_S)
#define INTERRUPT_CORE0_JPEG_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_JPEG_INTR_MAP_S  0
/** INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PPA_INTR_MAP_REG register
 *  PPA_INTR mapping register
 */
#define INTERRUPT_CORE0_PPA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
/** INTERRUPT_CORE0_PPA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PPA_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PPA_INTR_MAP_M  (INTERRUPT_CORE0_PPA_INTR_MAP_V << INTERRUPT_CORE0_PPA_INTR_MAP_S)
#define INTERRUPT_CORE0_PPA_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PPA_INTR_MAP_S  0
/** INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG register
 *  CORE0_TRACE_INTR mapping register
 */
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c)
/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_M  (INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_S)
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_S  0
/** INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG register
 *  CORE1_TRACE_INTR mapping register
 */
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0)
/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_M  (INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_V << INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_S)
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_S  0
/** INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_REG register
 *  DMA2D_IN_CH0_INTR mapping register
 */
#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4)
/** INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_S)
#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_S  0
/** INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_REG register
 *  DMA2D_IN_CH1_INTR mapping register
 */
#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8)
/** INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_S)
#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_S  0
/** INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_REG register
 *  DMA2D_IN_CH2_INTR mapping register
 */
#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac)
/** INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_S)
#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_S  0
/** INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_REG register
 *  DMA2D_OUT_CH0_INTR mapping register
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0)
/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_S)
#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_S  0
/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_REG register
 *  DMA2D_OUT_CH1_INTR mapping register
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b4)
/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_S)
#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_S  0
/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_REG register
 *  DMA2D_OUT_CH2_INTR mapping register
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b8)
/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_S)
#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_S  0
/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_REG register
 *  DMA2D_OUT_CH3_INTR mapping register
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1bc)
/** INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_S)
#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_S  0
/** INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_REG register
 *  PSRAM_MSPI_INTR mapping register
 */
#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c0)
/** INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_M  (INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_V << INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_S)
#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_S  0
/** INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_REG register
 *  HP_SYSREG_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c4)
/** INTERRUPT_CORE0_HP_SYSREG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_M  (INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_V << INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PCNT0_INTR_MAP_REG register
 *  PCNT0_INTR mapping register
 */
#define INTERRUPT_CORE0_PCNT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c8)
/** INTERRUPT_CORE0_PCNT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PCNT0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PCNT0_INTR_MAP_M  (INTERRUPT_CORE0_PCNT0_INTR_MAP_V << INTERRUPT_CORE0_PCNT0_INTR_MAP_S)
#define INTERRUPT_CORE0_PCNT0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PCNT0_INTR_MAP_S  0
/** INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PCNT1_INTR_MAP_REG register
 *  PCNT1_INTR mapping register
 */
#define INTERRUPT_CORE0_PCNT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1cc)
/** INTERRUPT_CORE0_PCNT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PCNT1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PCNT1_INTR_MAP_M  (INTERRUPT_CORE0_PCNT1_INTR_MAP_V << INTERRUPT_CORE0_PCNT1_INTR_MAP_S)
#define INTERRUPT_CORE0_PCNT1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PCNT1_INTR_MAP_S  0
/** INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_PAU_INTR_MAP_REG register
 *  HP_PAU_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d0)
/** INTERRUPT_CORE0_HP_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_PAU_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_PAU_INTR_MAP_M  (INTERRUPT_CORE0_HP_PAU_INTR_MAP_V << INTERRUPT_CORE0_HP_PAU_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_PAU_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_PAU_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_REG register
 *  HP_PARLIO_RX_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d4)
/** INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_M  (INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_V << INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_REG register
 *  HP_PARLIO_TX_INTR mapping register
 */
#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d8)
/** INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_M  (INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_V << INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_S  0
/** INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG register
 *  BUS_MONITOR_INTR mapping register
 */
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1dc)
/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_M  (INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S)
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S  0
/** INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_REG register
 *  MODEM_WIFI_MAC_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e0)
/** INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_REG register
 *  MODEM_WIFI_MAC_NMI_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e4)
/** INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_V << INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_REG register
 *  MODEM_WIFI_PWR_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e8)
/** INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_REG register
 *  MODEM_WIFI_BB_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ec)
/** INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_REG register
 *  MODEM_BT_MAC_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f0)
/** INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_REG register
 *  MODEM_BT_BB_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f4)
/** INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_REG register
 *  MODEM_BT_BB_NMI_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f8)
/** INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_REG register
 *  MODEM_LP_TIMER_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1fc)
/** INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_REG register
 *  MODEM_COEX_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x200)
/** INTERRUPT_CORE0_MODEM_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_V << INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_REG register
 *  MODEM_BLE_TIMER_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x204)
/** INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_REG register
 *  MODEM_BLE_SEC_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x208)
/** INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_REG register
 *  MODEM_I2C_MST_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20c)
/** INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_REG register
 *  MODEM_ZB_MAC_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x210)
/** INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_REG register
 *  MODEM_BT_MAC_INT1_INTR mapping register
 */
#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x214)
/** INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_S)
#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_S  0
/** INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_CORDIC_INTR_MAP_REG register
 *  CORDIC_INTR mapping register
 */
#define INTERRUPT_CORE0_CORDIC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x218)
/** INTERRUPT_CORE0_CORDIC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_CORDIC_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_CORDIC_INTR_MAP_M  (INTERRUPT_CORE0_CORDIC_INTR_MAP_V << INTERRUPT_CORE0_CORDIC_INTR_MAP_S)
#define INTERRUPT_CORE0_CORDIC_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_CORDIC_INTR_MAP_S  0
/** INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG register
 *  ZERO_DET_INTR mapping register
 */
#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x21c)
/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_M  (INTERRUPT_CORE0_ZERO_DET_INTR_MAP_V << INTERRUPT_CORE0_ZERO_DET_INTR_MAP_S)
#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_S  0
/** INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register
 *  LP_WDT_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x220)
/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M  (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_REG register
 *  LP_TIMER_REG_0_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x224)
/** INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_M  (INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_REG register
 *  LP_TIMER_REG_1_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x228)
/** INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_M  (INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MB_HP_INTR_MAP_REG register
 *  MB_HP_INTR mapping register
 */
#define INTERRUPT_CORE0_MB_HP_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x22c)
/** INTERRUPT_CORE0_MB_HP_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MB_HP_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MB_HP_INTR_MAP_M  (INTERRUPT_CORE0_MB_HP_INTR_MAP_V << INTERRUPT_CORE0_MB_HP_INTR_MAP_S)
#define INTERRUPT_CORE0_MB_HP_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MB_HP_INTR_MAP_S  0
/** INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_MB_LP_INTR_MAP_REG register
 *  MB_LP_INTR mapping register
 */
#define INTERRUPT_CORE0_MB_LP_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x230)
/** INTERRUPT_CORE0_MB_LP_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_MB_LP_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_MB_LP_INTR_MAP_M  (INTERRUPT_CORE0_MB_LP_INTR_MAP_V << INTERRUPT_CORE0_MB_LP_INTR_MAP_S)
#define INTERRUPT_CORE0_MB_LP_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_MB_LP_INTR_MAP_S  0
/** INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_REG register
 *  PMU_REG_0_INTR mapping register
 */
#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x234)
/** INTERRUPT_CORE0_PMU_REG_0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_M  (INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_V << INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_S)
#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_S  0
/** INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_REG register
 *  PMU_REG_1_INTR mapping register
 */
#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x238)
/** INTERRUPT_CORE0_PMU_REG_1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_M  (INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_V << INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_S)
#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_S  0
/** INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_REG register
 *  LP_ANAPERI_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x23c)
/** INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_M  (INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_V << INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_ADC_INTR_MAP_REG register
 *  LP_ADC_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x240)
/** INTERRUPT_CORE0_LP_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_ADC_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_ADC_INTR_MAP_M  (INTERRUPT_CORE0_LP_ADC_INTR_MAP_V << INTERRUPT_CORE0_LP_ADC_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_ADC_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_ADC_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_DAC_INTR_MAP_REG register
 *  LP_DAC_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_DAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x244)
/** INTERRUPT_CORE0_LP_DAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_DAC_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_DAC_INTR_MAP_M  (INTERRUPT_CORE0_LP_DAC_INTR_MAP_V << INTERRUPT_CORE0_LP_DAC_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_DAC_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_DAC_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_GPIO_INTR_MAP_REG register
 *  LP_GPIO_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x248)
/** INTERRUPT_CORE0_LP_GPIO_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP_M  (INTERRUPT_CORE0_LP_GPIO_INTR_MAP_V << INTERRUPT_CORE0_LP_GPIO_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG register
 *  LP_I2C_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24c)
/** INTERRUPT_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_I2C_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_M  (INTERRUPT_CORE0_LP_I2C_INTR_MAP_V << INTERRUPT_CORE0_LP_I2C_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_SPI_INTR_MAP_REG register
 *  LP_SPI_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_SPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x250)
/** INTERRUPT_CORE0_LP_SPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_SPI_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_SPI_INTR_MAP_M  (INTERRUPT_CORE0_LP_SPI_INTR_MAP_V << INTERRUPT_CORE0_LP_SPI_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_SPI_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_SPI_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_REG register
 *  LP_TOUCH_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x254)
/** INTERRUPT_CORE0_LP_TOUCH_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_M  (INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_V << INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_TSENS_INTR_MAP_REG register
 *  LP_TSENS_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x258)
/** INTERRUPT_CORE0_LP_TSENS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP_M  (INTERRUPT_CORE0_LP_TSENS_INTR_MAP_V << INTERRUPT_CORE0_LP_TSENS_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_UART_INTR_MAP_REG register
 *  LP_UART_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x25c)
/** INTERRUPT_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_UART_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_UART_INTR_MAP_M  (INTERRUPT_CORE0_LP_UART_INTR_MAP_V << INTERRUPT_CORE0_LP_UART_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_UART_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_UART_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_REG register
 *  LP_EFUSE_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x260)
/** INTERRUPT_CORE0_LP_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_M  (INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_SW_INTR_MAP_REG register
 *  LP_SW_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_SW_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x264)
/** INTERRUPT_CORE0_LP_SW_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_SW_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_SW_INTR_MAP_M  (INTERRUPT_CORE0_LP_SW_INTR_MAP_V << INTERRUPT_CORE0_LP_SW_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_SW_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_SW_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_TRNG_INTR_MAP_REG register
 *  LP_TRNG_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x268)
/** INTERRUPT_CORE0_LP_TRNG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP_M  (INTERRUPT_CORE0_LP_TRNG_INTR_MAP_V << INTERRUPT_CORE0_LP_TRNG_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_REG register
 *  LP_SYSREG_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x26c)
/** INTERRUPT_CORE0_LP_SYSREG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_M  (INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_V << INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register
 *  LP_APM_M0_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x270)
/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG register
 *  LP_APM_M1_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x274)
/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_REG register
 *  LP_APM_M2_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x278)
/** INTERRUPT_CORE0_LP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_REG register
 *  LP_APM_M3_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x27c)
/** INTERRUPT_CORE0_LP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_REG register
 *  LP_PERI0_PMS_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x280)
/** INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_M  (INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_REG register
 *  LP_PERI1_PMS_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x284)
/** INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_M  (INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_HUK_INTR_MAP_REG register
 *  LP_HUK_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x288)
/** INTERRUPT_CORE0_LP_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_HUK_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_HUK_INTR_MAP_M  (INTERRUPT_CORE0_LP_HUK_INTR_MAP_V << INTERRUPT_CORE0_LP_HUK_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_HUK_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_HUK_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
 *  LP_PERI_TIMEOUT_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28c)
/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_REG register
 *  LP_AHB_PDMA_IN_CH0_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x290)
/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_REG register
 *  LP_AHB_PDMA_IN_CH1_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x294)
/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_REG register
 *  LP_AHB_PDMA_OUT_CH0_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x298)
/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default:
 *  0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_REG register
 *  LP_AHB_PDMA_OUT_CH1_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x29c)
/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default:
 *  0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_REG register
 *  LP_SW_INVALID_SLEEP_INTR mapping register
 */
#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2a0)
/** INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
 *  Configures the interrupt source into one CPU interrupt.
 */
#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP    0x0000003FU
#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_M  (INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_V << INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_S)
#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_V  0x0000003FU
#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_S  0
/** INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default:
 *  0;
 *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
 *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
 *  feature with M-Level.
 */
#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL    0x00000003U
#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_S)
#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_V  0x00000003U
#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_S  8

/** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register
 *  reserved
 */
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2a4)
/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S : R/W; bitpos: [5:0]; default: 0;
 *  reserved
 */
#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S    0x0000003FU
#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_M  (INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_V << INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_S)
#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_V  0x0000003FU
#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_S  0
/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M : R/W; bitpos: [11:6]; default: 0;
 *  reserved
 */
#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M    0x0000003FU
#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_M  (INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_V << INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_S)
#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_V  0x0000003FU
#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_S  6

/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register
 *  Status register for interrupt sources 0 ~ 31
 */
#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2a8)
/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
 *  Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31.
 *  Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source triggered an interrupt
 *  1:No interrupt triggered
 */
#define INTERRUPT_CORE0_INT_STATUS_0    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_0_M  (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S)
#define INTERRUPT_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_0_S  0

/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register
 *  Status register for interrupt sources 32 ~ 63
 */
#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2ac)
/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
 *  Represents the status of the interrupt sources within interrupt-index-range 32 ~
 *  63. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source triggered an interrupt
 *  1:No interrupt triggered
 */
#define INTERRUPT_CORE0_INT_STATUS_1    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_1_M  (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S)
#define INTERRUPT_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_1_S  0

/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register
 *  Status register for interrupt sources 64 ~ 95
 */
#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2b0)
/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
 *  Represents the status of the interrupt sources within interrupt-index-range 64 ~
 *  95. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source triggered an interrupt
 *  1:No interrupt triggered
 */
#define INTERRUPT_CORE0_INT_STATUS_2    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_2_M  (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S)
#define INTERRUPT_CORE0_INT_STATUS_2_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_2_S  0

/** INTERRUPT_CORE0_INT_STATUS_REG_3_REG register
 *  Status register for interrupt sources 96 ~ 127
 */
#define INTERRUPT_CORE0_INT_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2b4)
/** INTERRUPT_CORE0_INT_STATUS_3 : RO; bitpos: [31:0]; default: 0;
 *  Represents the status of the interrupt sources within interrupt-index-range 96 ~
 *  127. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source triggered an interrupt
 *  1:No interrupt triggered
 */
#define INTERRUPT_CORE0_INT_STATUS_3    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_3_M  (INTERRUPT_CORE0_INT_STATUS_3_V << INTERRUPT_CORE0_INT_STATUS_3_S)
#define INTERRUPT_CORE0_INT_STATUS_3_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_3_S  0

/** INTERRUPT_CORE0_INT_STATUS_REG_4_REG register
 *  Status register for interrupt sources 128 ~ 159
 */
#define INTERRUPT_CORE0_INT_STATUS_REG_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2b8)
/** INTERRUPT_CORE0_INT_STATUS_4 : RO; bitpos: [31:0]; default: 0;
 *  Represents the status of the interrupt sources within interrupt-index-range 128 ~
 *  159. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source triggered an interrupt
 *  1:No interrupt triggered
 */
#define INTERRUPT_CORE0_INT_STATUS_4    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_4_M  (INTERRUPT_CORE0_INT_STATUS_4_V << INTERRUPT_CORE0_INT_STATUS_4_S)
#define INTERRUPT_CORE0_INT_STATUS_4_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_4_S  0

/** INTERRUPT_CORE0_INT_STATUS_REG_5_REG register
 *  Status register for interrupt sources 160 ~ 168
 */
#define INTERRUPT_CORE0_INT_STATUS_REG_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2bc)
/** INTERRUPT_CORE0_INT_STATUS_5 : RO; bitpos: [8:0]; default: 0;
 *  Represents the status of the interrupt sources within interrupt-index-range 160 ~
 *  168. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source triggered an interrupt
 *  1:No interrupt triggered
 */
#define INTERRUPT_CORE0_INT_STATUS_5    0x000001FFU
#define INTERRUPT_CORE0_INT_STATUS_5_M  (INTERRUPT_CORE0_INT_STATUS_5_V << INTERRUPT_CORE0_INT_STATUS_5_S)
#define INTERRUPT_CORE0_INT_STATUS_5_V  0x000001FFU
#define INTERRUPT_CORE0_INT_STATUS_5_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_0_REG register
 *  supervisor-mode PASS_IN status register for interrupt sources 0 ~ 31
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c0)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0 : RO; bitpos: [31:0]; default: 0;
 *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in supervisor-mode.
 *  1:The corresponding interrupt source is PASS in supervisor-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_1_REG register
 *  supervisor-mode PASS_IN status register for interrupt sources 32 ~ 63
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c4)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1 : RO; bitpos: [31:0]; default: 0;
 *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in supervisor-mode.
 *  1:The corresponding interrupt source is PASS in supervisor-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_2_REG register
 *  supervisor-mode PASS_IN status register for interrupt sources 64 ~ 95
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c8)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2 : RO; bitpos: [31:0]; default: 0;
 *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in supervisor-mode.
 *  1:The corresponding interrupt source is PASS in supervisor-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_3_REG register
 *  supervisor-mode PASS_IN status register for interrupt sources 96 ~ 127
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2cc)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3 : RO; bitpos: [31:0]; default: 0;
 *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in supervisor-mode.
 *  1:The corresponding interrupt source is PASS in supervisor-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_4_REG register
 *  supervisor-mode PASS_IN status register for interrupt sources 128 ~ 159
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2d0)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4 : RO; bitpos: [31:0]; default: 0;
 *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in supervisor-mode.
 *  1:The corresponding interrupt source is PASS in supervisor-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_5_REG register
 *  supervisor-mode PASS_IN status register for interrupt sources 160 ~ 168
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2d4)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5 : RO; bitpos: [8:0]; default: 0;
 *  Represents the supervisor-mode PASS_IN status of the interrupt sources with
 *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in supervisor-mode.
 *  1:The corresponding interrupt source is PASS in supervisor-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5    0x000001FFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_V  0x000001FFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_0_REG register
 *  machine-mode PASS_IN_M status register for interrupt sources 0 ~ 31
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2d8)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0 : RO; bitpos: [31:0]; default: 0;
 *  Represents the machine-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in machine-mode.
 *  1:The corresponding interrupt source is PASS in machine-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_1_REG register
 *  machine-mode PASS_IN_M status register for interrupt sources 32 ~ 63
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2dc)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1 : RO; bitpos: [31:0]; default: 0;
 *  Represents the machine-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in machine-mode.
 *  1:The corresponding interrupt source is PASS in machine-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_2_REG register
 *  machine-mode PASS_IN_M status register for interrupt sources 64 ~ 95
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2e0)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2 : RO; bitpos: [31:0]; default: 0;
 *  Represents the machine-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in machine-mode.
 *  1:The corresponding interrupt source is PASS in machine-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_3_REG register
 *  machine-mode PASS_IN_M status register for interrupt sources 96 ~ 127
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2e4)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3 : RO; bitpos: [31:0]; default: 0;
 *  Represents the machine-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in machine-mode.
 *  1:The corresponding interrupt source is PASS in machine-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_4_REG register
 *  machine-mode PASS_IN_M status register for interrupt sources 128 ~ 159
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2e8)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4 : RO; bitpos: [31:0]; default: 0;
 *  Represents the machine-mode PASS_IN status of the interrupt sources within
 *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in machine-mode.
 *  1:The corresponding interrupt source is PASS in machine-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_S  0

/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_5_REG register
 *  machine-mode PASS_IN_M status register for interrupt sources 160 ~ 168
 */
#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2ec)
/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5 : RO; bitpos: [8:0]; default: 0;
 *  Represents the machine-mode PASS_IN status of the interrupt sources with
 *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
 *  0:The corresponding interrupt source is not PASS in machine-mode.
 *  1:The corresponding interrupt source is PASS in machine-mode.
 */
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5    0x000001FFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_S)
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_V  0x000001FFU
#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_S  0

/** INTERRUPT_CORE0_CONFIG_STATE_REG register
 *  reserved
 */
#define INTERRUPT_CORE0_CONFIG_STATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2f0)
/** INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR : RO; bitpos: [0]; default: 0;
 *  reserved
 */
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR    (BIT(0))
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_M  (INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_V << INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_S)
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_V  0x00000001U
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_S  0
/** INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR : RO; bitpos: [1]; default: 0;
 *  reserved
 */
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR    (BIT(1))
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_M  (INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_V << INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_S)
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_V  0x00000001U
#define INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_S  1

/** INTERRUPT_CORE0_S_STATUS_REG register
 *  reserved
 */
#define INTERRUPT_CORE0_S_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2f4)
/** INTERRUPT_CORE0_INT_S_STATUS : RO; bitpos: [31:0]; default: 0;
 *  reserved
 */
#define INTERRUPT_CORE0_INT_S_STATUS    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_S_STATUS_M  (INTERRUPT_CORE0_INT_S_STATUS_V << INTERRUPT_CORE0_INT_S_STATUS_S)
#define INTERRUPT_CORE0_INT_S_STATUS_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_S_STATUS_S  0

/** INTERRUPT_CORE0_M_STATUS_REG register
 *  reserved
 */
#define INTERRUPT_CORE0_M_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2f8)
/** INTERRUPT_CORE0_INT_M_STATUS : RO; bitpos: [31:0]; default: 0;
 *  reserved
 */
#define INTERRUPT_CORE0_INT_M_STATUS    0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_M_STATUS_M  (INTERRUPT_CORE0_INT_M_STATUS_V << INTERRUPT_CORE0_INT_M_STATUS_S)
#define INTERRUPT_CORE0_INT_M_STATUS_V  0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_M_STATUS_S  0

/** INTERRUPT_CORE0_CLOCK_GATE_REG register
 *  Interrupt clock gating configure register
 */
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2fc)
/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
 *  Interrupt clock gating configure register
 */
#define INTERRUPT_CORE0_REG_CLK_EN    (BIT(0))
#define INTERRUPT_CORE0_REG_CLK_EN_M  (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S)
#define INTERRUPT_CORE0_REG_CLK_EN_V  0x00000001U
#define INTERRUPT_CORE0_REG_CLK_EN_S  0

/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register
 *  Version control register
 */
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc)
/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 38834448;
 *  Version control register
 */
#define INTERRUPT_CORE0_INTERRUPT_DATE    0x0FFFFFFFU
#define INTERRUPT_CORE0_INTERRUPT_DATE_M  (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S)
#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0x0FFFFFFFU
#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0

#ifdef __cplusplus
}
#endif
